3. CCD System Overview

Contents

3.1 Specifications and Requirements

Those functional requirements which were met (for readout of non-mosaic CCDs) by the HIRES/LRIS CCD system are marked with an asterisk (*).
  1. Two independent beams: Each beam of the spectrograph can be set up to expose and read out separately, or the two sides can be ganged together with a single command.

  2. Regular exposure mode (*): The shutter is opened for a specified period of time, it closes, and the CCD is read out. The minimum command-able non-dark exposure time is 0.1 s (the shutter will not be uniform for times less than about 1 second, but the data may be useful for bright objects) and the maximum time is 20,000 seconds. (Note: the minimum exposure time currently available on HIRES/LRIS is 1 second.)

  3. Multiple exposure mode with single readout (*): This involves N exposures of M seconds each, with a single readout at the end. The spectrograph may give or receive commands between each exposure. For example, DEIMOS may command the telescope to move between exposures and change either spectrograph or telescope focus, producing a focus sequence on one image. This mode is also useful to determine shutter timing error: a series of 1 second exposures in multiple mode is divided by a single regular exposure of the same total duration. The resultant is a map of the shutter timing error at 1 second.

  4. Multiple exposure mode with shift of image on the CCD by N rows (*): This mode is similar to item 3, but the image is now parallel-shifted N rows towards the serial register before the start of each sub-exposure. The data from the N top rows of each of these N-row shift-sequences are discarded. It may be faster in some cases to produce multiple exposures this way than by moving the telescope. It is also useful for tests within DEIMOS itself.

  5. Multiple exposure mode with shift of image on the CCD by N rows up and down: This mode is similar to item 4, but the image is now alternately parallel-shifted N rows towards or N rows away from the serial register before the start of each sub-exposure. For shift-sequences that shift rows towards the serial register, the data from the top N rows are discarded.

  6. Dark exposure: (*) Same as regular mode, but shutter remains closed.

  7. Bias exposure: A dark exposure of zero seconds.

  8. Specific amplifiers: The data are saved from only a specified subset of the amplifiers in the mosaic. This capability is primarily for diagnostic purposes, since a more generalized windowing capability will be provided for science images.

  9. Software selection between single- and dual-amplifier readout modes (*): Once a sufficient number of video processing boards is installed in the Science CCD controller (see Section 3.4.5 below), it must be possible to remotely switch between single and dual-amplifier readout mode under software control (as well as between either the left or right amplifiers if single-amplifier readout mode has been selected), without the need for changing any switches or jumpers at the controller. This selection will apply globally to all of the CCDs of the mosaic. The appropriate de-scrambling algorithms are applied to the interleaved pixel stream so that the displayed image is geometrically correct and has the correct handedness.

  10. Matched bias levels between CCD amplifiers: Mechanisms must be provided to insure adequate matching of the bias levels between amplifiers on the same CCD, as well as between CCDs that are part of the same mosaic. The goal is to get the bias level of all amplifiers in a mosaic equal to within 5 ADU. This match may be accomplished by both analog and digital adjustment. If needed, the software will provide a separate digital offset for each CCD channel.

  11. Matched gains between CCD amplifiers: Mechanisms must also be provided to insure adequate matching of the gains between amplifiers on the same CCD, as well as between CCDs that are part of the same mosaic. The goal is that all gains should match to within +/- 1%. If possible, this match should be accomplished by analog adjustment of the independent CCD bias voltages provided to each amplifier. (Note that adjustment of amplifier bias voltages will have some effect on read noise. However, we expect that the amount of bias level adjustment required to achieve balanced gains among the amplifiers is unlikely to make a significant change in read noise. Should this prove otherwise, the read noise requirement will not be sacrificed to achieve balanced amplifier gains.) It is expected that any such analog adjustments of the relative gains between amplifiers would be conducted in the laboratory and that a re-calibration of the absolute gain of the mosaic should be performed using an Fe55 X-ray source.

  12. Overscan regions (*): Provision will be made for reading a user-specified number of overscan pixels per row and overscan rows per image, and to optionally make these data available as part of the recorded image.

  13. Specific subregions: Read out only specific subregions of the mosaic. This mode will be used primarily during the slit mask alignment procedure. Since these readouts of the subregions are being used for alignment rather than detailed scientific analysis, pre-scan and over-scan pixels will not be retained in this readout mode. Furthermore, all of the subregions to be read out in a given exposure are subject to the following constraints: In the case where two sub-regions overlap each other, the readout software data pipeline will replicate the overlapped pixel data as needed.

  14. On chip-binning (*): Images can be binned on chip by 1 x 2, 2 x 1, and 2 x 2. Additional binning combinations will be supported, provided that these do not result in discontinuities in the image at the boundary which divides each row into the two halves that are read respectively by the amplifiers at each end. In general, values for column binning will be constrained to be evenly divisible into the sum of the number of prescan pixels per row plus the number of imaging pixels per row per amplifier (i.e., evenly divisible into {# of prescan pixels + 1024} if dual-amplifier readout mode, or into {# of prescan pixels + 2048} if single-amplifier mode). Values for row binning will be constrained to be evenly divisible into the number of rows (i.e., 4096). In the case of a binned and windowed readout, the window size will be adjusted upwards to insure that the binning parameters divide evenly into the corresponding dimension of the readout window.

  15. Rapid readout: A fast mode that pushes the CCD controller electronics and intervening data transmission paths as fast as they can go, with a concomitant increase in readout noise. This mode would be useful for focusing and alignment tests. The exact parameters of this mode remain TBD, since they depend on the characteristics of the selected CCD chip. The current controller design sets an upper limit of 3.2 microseconds/pixel if operating in single-amplifier readout mode, and 6.4 microseconds/pixel if operating in dual-amplifier readout mode when reading out the entire mosaic. If reading out only a subset of the CCDs in the mosaic, it may be possible to go a little faster.

  16. Software selectable gains (*): Four different system gains will be provided and made directly selectable by the observer. These four gains are provided by switching the gain of an amplifier in the video processing circuitry of the controller, and not by changing the bias voltages supplied to the CCDs. As currently implemented, the four gains provide amplifications of x1, x2, x4.75, and x9.5. The overall system gain (in e-/DN) achieved when x1 amplification is selected is TBD, and depends on the setting of CCD bias voltages. Such observer-accessible gain selection will be applied globally to the entire mosaic, and not to individual amplifiers.

  17. Statistics / diagnostic pipeline: As each image is read out and its pixel data are transmitted via the software pipeline, statistics will be computed "on-the-fly" to provide a brief summary of the number of defects or artifacts in the data, to assist the observer in making a rapid determination of image quality. Such statistics will include the number of saturated pixels, "dead" pixels, bad columns, etc. These statistics are described in more detail in section 8.4.1.3 of the DEIMOS Software PDR document, which is available on the web at

    http://www.ucolick.org/~sla/deimos/swpdr/imagereq.html.

  18. Eventual drift-scan mode: Optical studies show that distortion is low enough that drift-scanning may be a scientifically useful option. We did not engage in a full scale study of this option, but have tried to avoid design choices (such as consolidating the Science CCD Controller and Flexure Compensation CCD Controller into a common controller) that would either preclude or complicate its future addition. We will also study the possibility of a read-out mode similar to drift-scanning that might be used to reduce the effects of CCD fringing. However, we do not intend to implement drift-scanning for first light as that would require considerable extra software and testing, and the demand for it (as well as its feasibility) has not been proven. Were drift scanning to be added, it might be done as part of either the first or second year post-commissioning upgrades. Neither do we currently plan to implement the fringe-flattening readout mode for first-light.

  19. Readout noise: The readout noise requirement is 5 electrons at 100 Kpx/sec, with the goal to do significantly better if possible. This requirement is based on the calculation that the sky noise in the dimmest part of the spectrum for a moderate exposure (e.g., 2,000 seconds) at highest dispersion will be 10 electrons/px.

  20. Gain stability: The overall gain of the system should remain stable to 0.1% over a +/- 6 degree C ambient temperature change. This is primarily a function of the temperature stability of the components on the external preamplifier board, since the CCD controller electronics will be contained within a thermally-controlled enclosure, while the preamplifiers will not.

  21. Linearity of electronics: The linearity of the system should be within 0.5% up to the full range of the 16-bit ADC, which is 64K DN.

  22. A/D Converter Accuracy: The ADC will provide a resolution of 16-bits, with an accuracy of +/- 1 bit. A histogram of a digitized signal should confirm that there are no missing or preferred ADC codes.

  23. Bias frame flatness The signal level from bias frames should be flat across each row (including both the prescan and overscan regions) to within +/- 1 ADC unit.

  24. Limits on correlated noise in bias frames The Fourier spectrum of the signal obtained along any given (defect-free) row or column should be free of any significant peaks indicating periodic or correlated noise sources (e.g., 60 Hz noise from power lines, 20 KHz noise from switching supplies, etc.). The goal is that the Fourier amplitude of all components up to the Nyquist frequency should be less than 1 electron. To meet this specification, the average of the overscan pixels in each row may be subtracted first.

  25. Behavior on over-exposure The goal is that over-exposure of the chip by a signal level 100 times the full-well capacity should not produce any visible residual signal on an immediately subsequent exposure of 3600 sec duration. Note that this is only a goal. Ten seconds are allowed to purge between exposures.

  26. Cross-talk between different amplifiers Our goal is that a bright source should not produce a ghost that exceeds 1 x 10^-5 in any pixel.

  27. Readout times: The total time to read out, display, and store on disk an un-binned, full-frame CCD-mosaic raw exposure is estimated to be as follows: 
							Goal	Specification
							----	-------------
Read out CCDS						42s		120s

Transfer data from timing board to VME crate memory	 0s*		  0s*

Transfer data from VME crate to data taking computer	 0s*		  0s*

De-interleave pixel data and stitch into mosaic		 0s*		  0s*

On-the-fly statistics					 0s*		  0s*

Display raw image(s) on monitor(s)			 0s*		  0s*

Write raw image(s) to disk				13s		 20s

Total time					 	55s		140s
The CCD readout time goal of 42 seconds corresponds to a readout rate of 100 kilo-pixels/second/amplifier (or 10-microseconds/pixel/amplifier) with dual-amplifier readout per CCD chip, while the specification of 120 seconds corresponds to a 33 kilo-pixel/second/amplifier rate, which is comparable to the existing HIRES and LRIS systems. (The "goal" value is what we hope to achieve, and the "specification" value is the minimum that we plan to deliver.) The intervening processing steps between CCD readout and writing to disk are assigned zero time (and marked with *) to indicate that these operations are overlapped with the CCD readout using a similar data transmission and processing pipeline to that used for HIRES and LRIS.

If the image from the CCD mosaic is written to disk as a single file, then the writing to disk cannot be overlapped with the CCD readout because the mosaicked image must be completely de-interleaved and stitched together before disk writing operations can be initiated. In this case, the disk write time goal of 13 seconds assumes a sustained disk write rate of 20 megabytes/second, while the specification assumes a more conservative rate of 13 MB/sec. Either of these implies the use of RAID disk or disk striping technology.

The exact format in which the images are written to disk depends on both the selected readout mode and the disk format selected by the observer. Note that writing the mosaicked image to disk as a single image file allows the use of existing display tools for quick look analysis. While this is a useful option during initial testing and checkout of the instrument, it may not be the preferred format for recording actual science data. The various possible disk formats are described in detail Chapter 7 of the DEIMOS software PDR document (available via the web at

http://www.ucolick.org/~sla/deimos/swpdr/index.html#Chapter7)

In cases where the images from the individual CCDs of the mosaic are written to disk as separate files, it may be possible to overlap writing to disk with reading out of the mosaic, although our current software design does not provide for this overlap.

3.2 System Block Diagrams

Figure 3-1 (drawing number EL-3160-1D) shows a block diagram of the CCD system for a single beam of DEIMOS. The functions of the various components are briefly described below in Section 3.3 and covered in more detail in Chapters 4 through 7.

Figure 3-2 (drawing D0210.A) shows a simplified block diagram of the various data flows and associated bandwidth requirements for the DEIMOS CCD readout system. It also identifies a highest-case bandwidth requirement assuming a 10 microsecond/pixel read time and dual-amplifier readout from each CCD of the mosaic. It shows the dewars for both beams of the instrument, even though only one beam will be built for first-light. The functions of the various CCD controller boards are defined in the glossary (Section 3.6) below, and in Chapter 5. Chapter 6 covers the transmission of pixel data from the CCD controller to the data taking computer.

Figure 3-3 (drawing EL-3166-2D) provides a more detailed overview of the signal cabling between the CCD controllers, the detector vessel electronics boxes, and the wiring inside the detector vessel. This is discussed in more detail in Chapter 4.

3.3 Summary of Major Elements

The CCD system consists of the following major components (see Figure 3-1 ):

3.3.1 Detector Vessel

The Detector Vessel contains:

The CCD mosaic is used to obtain either direct images or spectra. For direct images, only the top four CCDs of the mosaic are used (the blue end of the spectral range), while for spectra the entire mosaic is used.

The flexure compensation CCDs are used as sensors in a low-speed servo loop to compensate for changing instrument flexure as the DEIMOS instrument rotates (see Chapter 7).

The CCD mosaic is mounted to a cold backplane whose temperature is controlled via the heater resistors attached to the cold strap. The two flexure compensation CCDs are mounted to the same backplane and are located along the two open sides of the mosaic.

A short cable carries the signals from each CCD to its own CCD Interconnect Board located inside the detector vessel. A coupling capacitor mounted on this board provides AC-coupling between the output amplifier of the CCD and the input to the external preamplifier located in the detector vessel electronics box (see section 3.3.2 below). Each CCD has two output amplifiers, and the detector vessel is wired to provide for independent operation of these amplifiers.

All the CCDs are mounted on a common backplane that has two axes of motion. Each axis is driven by its own external servo motor via vacuum-tight mechanical feed-throughs. One axis controls the piston of the backplane and is used to adjust the detector focus. The other axis moves the backplane in translation in the X direction and is used for one axis of the flexure compensation servo loop. The Y axis of the flexure compensation servo is adjusted via the tent mirror, which is not directly a part of the CCD/dewar system.

The two external servo motors attached to the detector vessel are controlled via a Galil DMC-1500-series motion controller. Software running on the data taking computer and the supervisory computer (not shown in block diagram but attached to the same 10-Mb/sec network as the data taking computer) sends commands to the Galil controller via the 10-Mb/sec ethernet network and the Lantronix ETS8P terminal server, which converts these commands to the RS-232 serial format used by the Galil controller.

3.3.2 Detector Vessel Electronics Boxes

There are three Detector Vessel Electronics boxes. Two of these service the CCD mosaic, with each box handling the signals from one half of the mosaic. The third services the signals from the two flexure compensation CCDs. Each CCD box contains: The dual-channel preamplifier boards are used to amplify the signals from each of the CCD output amplifiers. This preamplification is needed since these signals must drive 6 feet of cable to reach either the Science CCD controller or the Flexure Compensation CCD controller. Each of the two output amplifiers of a CCD is AC-coupled to the input of one of the two channels of a preamplifier board via one of the two coupling capacitors located on each CCD's Interconnect Board mounted inside the detector vessel. One dual-channel preamplifier board services the two output amplifiers for a given CCD (See Figure 4-?).

The analog switch board provides a means of electrically isolating the mosaic CCDs and flexure compensation CCDs from the outside world. All of the clock waveforms and bias voltages that originate from the CCD controller must first pass through the analog switches on this board before reaching the CCDs. This provides a means by which we can verify that all of the clocks and bias voltages are at the correct voltages levels before we allow them to be applied to the CCDs. The analog switches on this board also protect the CCDs from accidental electrostatic discharge when the detector vessel is being handled or when cables are being connected or disconnected from the outside of the detector vessel electronics box. The analog switch board also contains filters for providing a final level of filtering to the bias voltages (particularly the output drain voltages) to reduce noise.

The power-filtering boards provide a final level of filtering to the +15 and -15 volts used to power the external preamplifier boards, so as to reduce noise in the preamplifiers. They also filter the +5, +15, and -15, and +36 volts supplied to the analog switch boards.

3.3.3 Science CCD Controller

The Science CCD controller

The Science CCD controller is implemented using a combination of first and second-generation SDSU CCD controller boards, as well as some boards developed at UCO/Lick. A more detailed description of the second-generation SDSU CCD controller boards is provided in Chapter 5 as well as in the SDSU documentation (which can currently be found at http://mintaka.sdsu.edu/ccdlab/intro2.html).

The Science CCD controller consists of the following boards, most of which are shown in Figure 3-4 (drawing EL-3161-1D):

3.3.3.1 Timing Board (1)
The timing board provides the overall control and directs the operations of other boards in the system. The timing board provides the timing of all of the waveforms generated by the CCD controller.

All external communication with the CCD controller takes place through the timing board. The timing board receives external commands and transmits back status and digitized CCD pixel data via a dual-fiber fiber-optic interface which connects to a fiber interface board on the Science CCD VME crate.

3.3.3.2 Utility Board (1)
The utility board is responsible for various moderate-speed utility functions such as exposure timing and shutter control, plus control and monitoring of the CCD detector temperature and CCD controller enclosure temperature. The utility board also provides general purpose analog and digital I/O, which can be used for monitoring power supply voltages as well as the voltage levels of the clock waveforms and bias voltages generated by the other boards in the controller.

3.3.3.3 Clock Generation Boards (5)
The clock generation boards, under control of the timing board, generate the clock waveforms used to clock charge out of the CCDs. Each clock generation board can generate 24 clock signals. The high and low levels of each clock signal can be independently programmed to voltages between -10 and +10 volts. Multiple clocks can be switched between states simultaneously, and state changes can be commanded every 40 nanoseconds.
3.3.3.4 Video Processing Boards (4-8)
The video processing boards, under control of the timing board, perform the video processing and digitization of the CCD video signal. They return each 16-bit digitized pixel value to the timing board. The video processing boards also generate the CCD bias voltages that are supplied independently to each CCD of the mosaic and their respective amplifiers. Each video processing board has two independent signal processing chains and can thus handle the video signals from two CCD output amplifiers.

Note that the standard second-generation SDSU video processing board is designed for direct connection from the CCD output amplifier to a DC-coupled input of a preamplifier located on the video processor board. That design assumes that the CCD controller (and its video processor board) can be located in close proximity to the detector. Due to the instrument packaging constraints of DEIMOS this is not possible, so we require an external preamplifier that is mounted close to the detector. Also, the DEIMOS CCD signal chain is AC-coupled rather than DC-coupled. Accordingly, DEIMOS will be using a version of the SDSU video processing board that has been modified to work with an external, AC-coupled preamplifier.

3.3.3.5 Power Monitor Board (1)
The power monitor board is a UCO/Lick designed board that employs a series of voltage comparator chips interfaced via PAL logic to continuously monitor the status of the +5, +15, -15V, and +36V power supplies, as well as the status of the incoming 110-volt AC power. If the power monitor board detects that any of these voltages have gone out of range, it removes the enable signal from the analog switches in the CCD detector vessel electronics boxes, thus electrically disconnecting the CCDs from the clocks and bias voltages supplied by the CCD controller. Although this board is somewhat similar in function to a power monitor board provided by SDSU, it uses a significantly different implementation.

3.3.4 Flexure Compensation CCD Controller

The Flexure Compensation CCD controller

We initially considered consolidating the Flexure Compensation CCD controller into the Science CCD controller, because the mosaic CCDs and the flexure compensation CCDs usually do not need to be read out at the same time. Since the shutter to the detector is normally closed during readout of the mosaic CCDs, there is no point in reading out the flexure compensation CCDs during mosaic readout, since the flexure compensation CCDs will not see any light. Since the flexure compensation CCDs need only be read out when they are illuminated, and since the mosaic CCDs are not normally read out when the shutter is open, the mosaic CCDs would normally not be read out during readout of the FC CCDs.

However, if drift scanning is ever implemented for DEIMOS, the mosaic CCDs and flexure compensation CCDs may need to be read out at the same time. In addition, during our test and development phase, we will simultaneously need to operate in two different locations (the Lick Instrument Lab and the Lick CCD Lab) two different dewars (the DEIMOS dewar and a test dewar) containing full and partially-populated mosaics, as well as flexure compensation CCDs. By keeping the Flexure Compensation CCD controller as a separate controller from the Science CCD controller, and by using the same basic architecture for both, we can address both of these needs.

The Flexure Compensation CCD controller is implemented using a combination of first and second-generation SDSU CCD controller boards, as well as some boards developed at UCO/Lick. It is similar in design to the Science CCD controller but will require significantly fewer controller boards since it has fewer CCDs and amplifiers to operate. However, we will provide sufficient slots and interconnect cabling so that by shuffling controller boards between the two controllers we can use both to operate partially- populated mosaics.

The Flexure Compensation CCD controller will probably consist of the following boards:

3.3.5 Science CCD VME Crate

The Science CCD VME Crate serves as a buffer and protocol converter between the Science CCD controller and the data taking computer. It simplifies future upgrades and/or replacement of the data taking computer, since our custom (i.e., non-industry-standard) SDSU fiber-optic interface is installed in the VME crate rather than the data taking computer. (This design goal is discussed in "CCD Data Acquisition Systems at Lick and Keck Observatories", by Kibrick, Stover, and Conrad, pgs. 277-288 in ADASS II, ASP Conference Series, Vol. 52, 1993, Hanisch, Brissenden, Barnes, eds., and which can be found on the web at

http://www.ucolick.org/~kibrick/deimos/ccddas.ps.)

The Science VME Crate consists of a 3U-high chassis containing a horizontally-mounted 5-slot J1/J2 VME backplane. Installed in that backplane is one SDSU fiber-optic interface board (VMEINF) for each timing board in the Science CCD controller. Each timing board connects to its corresponding fiber-optic interface board in the Science VME crate via a dual-fiber-optic cable.

The Science VME Crate also contains an embedded CPU board (a Force CPU 5CE) and a 256MB VME memory board. This large memory board allows us to buffer a complete CCD mosaic image in the Science VME Crate. An industry-standard high-speed network interface (i.e., 100-Mbit/sec fast-ethernet) connects the embedded CPU in the Science VME crate with a matching network interface in the data taking computer, allowing high speed transfer of images from the Science VME crate to the data taking computer. The embedded CPU board can either run the VxWorks real-time kernel (like HIRES, LRIS, and MOS) or a Unix operating system, including either SunOS or Solaris. Our default plan is to run Solaris in this board, but VxWorks is available as a fallback.

3.3.6 Flexure Compensation CCD VME Crate

The Flexure Compensation CCD VME Crate performs the same function for the Flexure Compensation CCD Controller as the Science CCD VME Crate performs for the Science CCD Controller. The Flexure Compensation CCD VME Crate will likely use identical hardware to what is used in the Science CCD VME Crate in order to simplify sparing and swapping of components to facilitate troubleshooting, even though the Flexure Compensation CCD VME Crate does not need as much VME memory or a high-speed network interface.

3.3.7 Data Taking Computer

This is the computer at which the astronomer sits, and which receives the CCD images from the Science and Flexure Compensation CCD controllers via the industry-standard network interfaces from their respective CCD VME crates. The data taking computer displays the CCD images in real-time as they are being read from the CCD detectors, and records these images to disk when the readout is complete. Additional discussion of the data taking computer is provided in Chapter 6. (As soon as this chapter becomes available, it will be posted to the web at

http://www.ucolick.org/~kibrick/deimos-ccd/chapter6.html)

3.4 Decisions Since Previous Reviews

Preliminary design proposals for the DEIMOS CCD system were reviewed at the DEIMOS Optical, Mechanical, Electrical PDR held in November 1994 (see Chapter 4 of that PDR document) and the DEIMOS Software PDR held in March 1996 (see Chapter 6 of that PDR document, available via

http://www.ucolick.org/~kibrick/deimos/chapter6.html).

Several design questions explored during those reviews have either now been settled or will likely be settled by the date of this review (May 20, 1997):

3.4.1 Selection of CCD controller hardware

At the 1994 DEIMOS review, various CCD controller hardware options were considered (e.g., NOAO/ARCON, ESO, SDSS, SDSU-1), and a clear case was presented for using the CCD controller hardware developed by Bob Leach of the Astronomy Department of San Diego State University (SDSU). The default plan presented at that review was to use a second-generation SDSU CCD controller system, which was then at a very early stage of development. In case this second-generation system did not develop as planned, the fall-back plan was to use a scaled-up version of the first-generation SDSU CCD controller hardware. This is the same type of hardware as was used by both Keck-1 optical instruments: the HIRES Resolution Echelle Spectrometer (HIRES) developed at UCO/Lick, and the Low Resolution Imaging Spectrograph (LRIS) developed at Caltech.

At the 1996 DEIMOS software PDR, we described various difficulties we had identified with scaling-up the first-generation SDSU hardware (e.g., bus length/termination issues, DSP memory constraints, synchronization of multiple timing boards, etc.). We proposed continuing with the second- generation SDSU hardware (then still under active but somewhat delayed development) as the default plan, provided that it became available in time to meet the DEIMOS schedule. The review board from that PDR strongly endorsed this plan and encouraged us to defer further effort on the fall-back plan as long as possible.

Earlier this year, we received our first complete set of beta-test boards for the second-generation SDSU CCD controller and are currently conducting tests to evaluate its performance. Preliminary test results are encouraging, and the second-generation design appears to have resolved many of the limitations of the first-generation design which had made it difficult to scale-up for use with the DEIMOS mosaic. Unless our remaining tests identify significant problems, the second-generation SDSU hardware will be used to construct the CCD controller for the DEIMOS mosaic. The detailed designs for this controller (presented in Chapter 5) assume the use of this hardware.

A major goal of this design review is to secure the Review Board's endorsement of our selection of this hardware. Our current plan is to proceed with purchase of the first major complement of this hardware as soon as this endorsement is obtained.

3.4.2 Matching of video bias levels from each amplifier signal chain

Under item 10 of the functional requirements in Section 3.1, the bias levels between the various amplifiers used to read out the DEIMOS CCD mosaic must be matched within 5 ADU. Accordingly, the software will provide a separate digital offset value for each amplifier which will be subtracted from each pixel during its transmission to the data taking computer, either by the timing board software or the software running in the VME crate. This digital offset value for each amplifier will be adjustable by the observer, to allow for compensation of small drifts in the bias level which may occur over time. While the second-generation analog boards may provide sufficient resolution in the adjustment of this bias level to make this separate software-based digital adjustment unnecessary, we plan on implementing it anyway.

3.4.3 Matching of gains from each amplifier signal chain

At the DEIMOS software PDR, several options were explored for meeting our goal to match the gains of all amplifiers in the mosaic to within 1%. These options included: a) independent adjustment of bias voltages to each amplifier, and b) re-scaling the digitized pixel values via a floating multiplication followed by rounding to an integer value.

The consensus of that review was that "attempting to match the CCD amplifier gains to 1% may never be possible and software to correct the inequalities probably will be needed. Thus, the hardware requirement likely can be relaxed if the software is designed to compensate from the outset."

However, given that the second-generation SDSU controller hardware provides an order of magnitude improvement (over the first-generation hardware) in the resolution to which bias voltages can be adjusted, option a may prove feasible. By the time of the this review (May 20), we should have measurements for the MIT-Lincoln Labs CCDs indicating just how precisely we can make gain adjustments given the resolution of bias voltage adjustments provided by the second-generation SDSU hardware.

3.4.4 New preamplifier design without on-board DC-restoration circuit

At the 1994 DEIMOS review, the preliminary design for the preamplifier circuit specified that an active DC restoration mechanism would be provided on the preamplifier to discharge the dewar coupling capacitor during each pixel time. The new preamplifier design described in Chapter 4 eliminates the need for this mechanism.

3.4.5 Dual-amplifier readout mode

At the 1996 DEIMOS software review, the question of whether or not to design for dual-amplifier readout mode received considerable discussion. Given the significant added hardware costs of providing this capability and the considerable uncertainty as to whether it will provide any net benefit, the review board encouraged us to focus on providing single-amplifier readout, but to leave hooks that would allow for eventual upgrade to dual-amplifier operation should that prove feasible.

Our current CCD controller design provides this flexibility via a phased implementation plan. The detector vessel wiring and controller interconnect cabling will be fabricated to provide for dual amplifier readout. However, during the first phase of implementation, we will purchase only enough CCD controller boards to allow for single-amplifier operation of all 8 CCDs of the mosaic, and most of our initial tests of the full mosaic will be conducted in this mode.

The interconnect cabling scheme provides sufficient flexibility so that with a simple re-arrangement of cables this limited number of controller boards can be used to operate a subset of the mosaic in dual-amplifier readout mode. This will allow us to conduct tests on CCDs selected for the DEIMOS mosaic to determine whether the advantages of dual-amplifier readout mode (i.e., potential reduction in overall readout time, but only if all CCDs have two working amplifiers) outweigh the possible disadvantages (e.g., crosstalk between same-chip amplifiers, saturation of various data paths).

If and when the feasibility and utility of dual-amplifier operation is established for the CCDs used in the DEIMOS mosaic we will proceed to the second phase of implementation and purchase the remaining CCD controller boards needed to provide for dual-amplifier operation of the full mosaic.

A more detailed discussion of the controller design, phased implementation plan, and the various tradeoffs between single and dual-amplifier readout modes is provided in Chapter 5.

3.4.6 100-Mbit/sec fast ethernet selected for link from CCD VME crate

At the 1994 and 1996 DEIMOS reviews, our overall system block diagram left open the question of what type of high-speed network link would be used to transfer data from the Science CCD VME crate to the data taking computer. We have now selected 100-Mbit/sec twisted-pair fast ethernet for this link, and have conducted tests demonstrating that it provides the needed bandwidth. Addition details are provided in Chapter 6.

3.4.7 Force 5CE CPU board selected for use with CCD VME crate

At the 1994 and 1996 DEIMOS reviews, the CPU board in the Science CCD VME crate was not specified. The Force 5CE CPU board has now been selected for this purpose and for use in the Flexure Compensation CCD VME Crate. This board is capable of running a variety of systems, including Solaris, SunOS, and VxWorks. Our current plan is to run Solaris on this board and to have it boot from the data taking computer. Additional details are provided in Chapter 6.

3.5 Outstanding Issues/Concerns

3.5.1 SDSU VMEINF-2 board still under development.

We have now operating a complete set (timing, clock generation, and video processing) of beta-test boards for the second-generation SDSU CCD controller. These are interfaced to an existing first-generation fiber interface (VMEINF-1) board in the Science CCD VME Crate. While this current arrangement works satisfactorily for our initial tests, the existing VMEINF-1 board will not allow us to realize the full bandwidth capability of the second-generation SDSU CCD controller.

A second-generation fiber interface board (VMEINF-2) is currently under development at SDSU, with delivery of a beta-test version of this board anticipated in August. As long as there are not significant slips in this schedule, it should not impact our DEIMOS development effort. However, should problems arise in the completion of this board, we might need to scale back the bandwidth of the DEIMOS CCD system, which will increase the time required to readout the DEIMOS mosaic. The magnitude of this increase depends on the readout mode in use (single- or dual-amplifier) and the selected signal integration time.

Should delivery of the VMEINF-2 board be delayed, it may be possible to test the full bandwidth capability of the second-generation SDSU CCD controller using a borrowed Sbus fiber interface board. This board could be installed temporarily in an available Sbus slot on the CPU board in the CCD VME crate, or in an available Sbus slot of a Sun-architecture data taking computer.

3.5.2 Driving a large number of boards from a single timing board

Based on the careful attention to the design of the bus interface logic in the second-generation SDSU CCD controller, we do not anticipate problems with driving a full complement of boards (8 video processing and 5 clock generation boards) from a single second-generation timing board. However, this capability has not yet been proven, and we may be the first group to attempt this proof. Should problems arise in this area, they most likely can be resolved by slowing down various bus transactions by means of inserting wait states via changes to the DSP startup software that initializes various hardware wait state registers in the DSP. Insertion of such wait states may result in some reduction in system bandwidth.

Should problems arise in this area which cannot be resolved via insertion of wait states, then significant re-design of the DEIMOS CCD controller might prove necessary, so as to reduce the number of clock generation and/or video boards driven by a single timing board. This would require operation of multiple timing boards, which would then need to be synchronized in order to prevent the noise generated by asynchronous operation. While the second-generation SDSU CCD controller provides hardware features for synchronizing the operation of multiple timing boards, these features are as yet also untested. Operation of multiple timing boards in the CCD controller also has downstream impacts on the hardware required in the Science CCD VME crate and would require the addition of a VMEINF board for each timing board added to the CCD controller.

One risk of our phased implementation plan is that it currently defers until phase 2 a test of whether a second-generation SDSU timing board can successfully operate a CCD controller fully populated with sufficient boards to operate the full DEIMOS CCD mosaic in dual-amplifier readout mode. Thus, it would be advisable for us to temporarily obtain a full complement of boards (e.g., either on loan from SDSU or by borrowing from other projects) in order to conduct this test during phase 1.

3.5.3 Adjusting system gain for low-noise hi-gain CCDs

Some CCDs have on-chip amplifiers with very high gain (e.g., .25e-/DN) when they are operated to achieve the lowest possible noise (e.g., 1.1e-/DN). The MIT-LL 2K by 4K CCDs are in this category. At such high gains, the 16-bit ADC converter will reach its maximum count of 64K for a signal of only 16Ke-. Many observers may want to operate with a lower gain (by lowering the output drain bias voltage) to obtain better dynamic range at the cost of increased noise.

Depending on the CCDs used for DEIMOS, it might be possible to make relatively large (e.g., a factor of 2) gain changes by allowing the observer to adjust (within a limited, safe range) the output drain bias voltage. This adjustment mechanism could be implemented two different ways:

  1. Allow the observer to select between a discrete set of pre-calibrated output drain bias voltages whose resulting gains have already been accurately calibrated using an Fe55 Xray source. In this case, the observers would not be allowed to manipulate the output drain bias voltage directly. This implementation would require that we measure in the lab all combinations of gain settings that result both from this discrete set of output drain bias voltages and from the discrete set of gain settings provided by the video processing circuitry in the SDSU CCD controller.

  2. Allow the observer to adjust the output drain bias voltage directly (within a safe range of voltages), and leave it to the observer to calibrate the corresponding gain at that voltage. Provided that there is at least one standard output drain voltage that has been accurately calibrated against the Fe55 Xray source and can thus be used as a reference, the observer could then calibrate other OD voltages via observations of a standard star obtained at both the reference OD voltage and the adjusted OD voltage. However, this scheme presents significant problems with respect to insuring that these observer-calculated gains are accurately recorded in the FITS headers of the science data.

In either case, we are entering into unknown territory, since in all of our existing CCD systems we fix the output drain bias voltage at some optimal value, calibrate the system gain, and then never change it. There may be unexpected consequences of dynamically changing the output drain voltage during the course of observing.

The overall gain of the system can be adjusted by:

When operating low-noise hi-gain devices such as the MIT-LL CCDs, we need to carefully determine which combination of adjustments can best be used to lower the overall system gain so as to increase the dynamic range.

3.5.4 Cross-talk between same-chip amplifiers

If a given type of CCD exhibits unacceptably high cross-talk between amplifiers on the same chip, then implementing dual-amplifier readout mode for such CCDs may not be worthwhile. Since measurements of such cross-talk can be made as soon as the first few CCDs of each type become available for evaluation, they might provide an early indication of the costs and benefits associated with implementing dual-amplifier readout mode. Accordingly, as different types of chips become available for testing, we should be certain to obtain measures of crosstalk across the range of parameters (e.g., gain and per-pixel read rate) over which these CCDs are likely to be operated in the DEIMOS mosaic.

If the CCDs selected for the DEIMOS mosaic exhibit negligible same-chip cross-talk, then we need to determine the minimum signal integration time required to meet our 5e- (at 100 Kpx/sec) readout noise requirement. If that signal integration time puts us into the regime where dual-amplifier readout would result in reduced readout time (see Section 5.1), then we should press even harder to get 8 CCDs all of which have two usable amplifiers.

Alternatively, if the selected CCDs exhibit same-chip cross-talk problems that are intractable, we should consider deferring further effort on the dual-amplifier readout mode, and consider accepting CCDs which have only one working amplifier but which in other respects might be superior to CCDs with two working amplifiers.

3.6 Glossary 


ADU		- Analog/Digital Unit, sometimes also referred to as DN, for
		  digital number.  These correspond to one resolution unit of
		  the analog to digital converter used to digitize the CCD
		  signal.

Clock Driver	- In the second-generation SDSU CCD controller systems,
Board		  the functions of the first-generation analog board have
		  been split between this board and a separate video
		  processing Board.  The clock driver board (in response
		  to commands sent from the timing board) generates the
		  analog voltages used for CCD Clock waveforms.  This
		  board is also referred to as the clock generation board.

DAC		- Digital to analog converter: a device used to generate
		  an analog voltage from a digital input.

DSP		- Digital signal processor: a high-speed microprocessor chip
		  optimized for signal processing application.  The SDSU CCD
		  controllers use Motorola 56000-series DSP chips.

fast-ethernet	- An updated ethernet protocol which operates at 100 megabits
		  per second rather than at the 10 megabits/second of
		  conventional ethernet.

ESI     	- Echellette Spectrograph and Imager, currently under
          	  development at Lick for installation on Keck 2

GUI		- Graphical User Interface

HIRES		- High Resolution Echelle Spectrometer built at Lick and
          	  now in use on Keck I

Leach controller- The SDSU CCD controller is sometimes referred to as the
		  Leach CCD Controller.  Bob Leach prefers that the former
		  name be used.

LIRC2		- Lick Infrared Camera, built at Lick and used on both the
		  Shane 3-m and Nickel 1-m telescopes at Mt. Hamilton.

LRIS		- Low-Resolution Imaging Spectrograph built at CIT and
		  now in use on Keck I.  This spectrograph, like DEIMOS,
		  employs multi-aperture slit masks and also shares
		  some similarity in optical design

MOS		- Fiber-fed prime-focus Multi-Object Spectrograph now
		  being commissioned on Shane 3-m telescope at Lick

overscan pixels - An arbitrary number (0 to N) of non-image pixels which can
		  be read out at the end of each CCD row by continuing to
		  shift the serial shift register after all of the image
		  pixels have been shifted out.  Overscan pixels are often
		  used for CCD baseline compensation or other low-level
		  engineering purposes.


overscan rows-	  An arbitrary number (0 to N) of non-image rows  which can
		  be read out after the image data have been 
		  shifted out of the CCD chip.  The reading of over overscan
		  rows includes both parallel and serial transfer.  Overscan
		  rows are sometimes used for CCD baseline compensation or
		  other low-level engineering purposes.

PFCAM   	- Prime Focus Camera, currently under development at
          	  Lick for installation on the Shane 3-m telescope

prescan pixels  - A fixed number of CCD pixels at the beginning of each CCD
		  row which have been masked on the CCD chip itself so that
		  they receive no light.  The number of prescan pixels is set
		  by the design of a given CCD.  These pixels are often used
		  for CCD baseline compensation or for other low-level
		  engineering tests.

prescan rows	- An arbitrary number (0 to N) of non-image rows which can
		  be read out immediately prior to the readout of an image.
		  The reading of prescan rows includes only serial transfer,
		  and thus can be used to independently measure serial
		  transfer noise.  Prescan rows are used primarily for
		  low-level engineering tests.

RAID		- Redundant Arrays of Inexpensive Disks.  The name for a
		  technology which combines many separate, relatively slow
		  and small disks into a device which appears to be a single,
		  large, fast disk.

Sbus		- A computer interface bus found inside of Sun Sparc
		  architecture computers into which relatively small and
		  inexpensive interface boards can be plugged.  A typical
		  Sun Sparc computer usually has at least one, and sometimes
		  several available Sbus slots.

SDSS		- Sloan Digital Sky Survey

SDSU		- San Diego State University

SDSU CCD 	- The CCD controller system developed by Bob Leach of the
controller	  Astronomy Department at San Diego State University.  The
		  second-generation of this controller is now in beta-test.

Timing Board	- In both the first- and second-generation SDSU CCD controller
		  systems, the timing board provides the overall control and
		  system synchronization and directs the operations of the
		  other boards in the system.  The timing board receives
		  external commands and transmits back status and digitized
		  CCD pixel data via a dual-fiber fiber-optic interface.

Unix 		- A Unix operating system, which varies in form depending on
		  the underlying hardware architecture and/or vendor.  In the
		  context of the VME crate for DEIMOS, the specific version
		  will most probably be Solaris 2.x.

Utility Board	- In both the first- and second-generation SDSU CCD controller
		  systems, the utility board (in response to commands sent
		  from the timing board) handles various utility functions
		  such as exposure timing and shutter control, plus control
		  and monitoring of CCD detector temperature  and CCD controller
		  enclosure temperature.  In HIRES, the utility board was also
		  involved in the control loop which automatically refills the
		  dewar with liquid nitrogen as needed, but that function will
		  be done elsewhere in DEIMOS.

Vdd		- CCD Output Drain bias voltage, also often abbreviated as OD.
		  This bias voltage has a profound impact on both the gain and
		  read noise of the output amplifier and on some CCDs can be
		  used effectively to adjust the output gain over a relatively
		  wide range.  However, it is vital that this voltage not be
		  adjusted above the maximum rated value for the chip.

Video Processing- In the second-generation SDSU CCD controller systems,
Board		  the functions of the first-generation analog board have
		  been split between this board and a separate clock driver
		  board.  The video processing board (in response to commands
		  sent from the timing board) performs the video processing
		  of the CCD signal and the analog to digital conversion of
		  that signal, returning the digitized value to the timing
		  board.  This board also generates the CCD bias voltages.

VME Board	- A circuit board which conforms to the mechanical and
		  electrical standards of the VME Bus Specification and which
		  plugs into a slot of a VME backplane inside of a VME chassis.

VxWorks		- A real-time kernel which was used in the VME crates for
		  HIRES and LRIS, as mandated by a Keck-1 standard.  VxWorks
		  is not a standard for Keck-2 instruments.